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In a conventional dynamic random access memory (DRAM) system, a read training is required to be performed to optimize timing between data signals and a data strobe signal. When the read training operation is executed, however, all of the data pins (DQ pins) are required to be toggled or driven to obtain the timing information, causing more power consumption.

In the embodiments of the present invention, the clock timing information between the data signal and the clock signal (data strobe signal) can be simply obtained, and the power consumption can be improved because not all of the data terminals (data pins) are driven or toggled during the training operation.

The memory module is characterized in that when the training signal generator transmits the training signal to the memory controller through the specific terminal (N_DQS'), all of the data terminals (N_DQ') are not toggled or driven